[Libre-soc-isa] [Bug 1183] add /mrr mode (reverse mode) to Data-Dependent Fail-First CR_ops

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1183

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #1)

> are you sure it covers sv.cmpi? cmpi has BF as the destination field which
> is 3 bits, not 5.

arse. you're right.

> (In reply to Luke Kenneth Casson Leighton from bug 1044 comment #56)

> though, now that I look at it more closely, do we need SNZ that much?

yes. it provides the boolean-logic equivalent of AND OR NAND and NOR.
i learned this trick on thinking through the design of sv.bc. have
a look and you'll see why it's important.

damnit i hate doing redesigns of SV this late in the game.

 |6 | 7 |19:20|21 | 22:23   |  description     |
 |--|---|-----|---|---------|------------------|
 |RG|SNZ|0  0 |/  | dz  sz  | simple mode                      |
 |RG|SNZ|1  0 |/  | dz  sz  | scalar reduce mode (mapreduce) |
 |RG|SNZ|VLI 1|inv|  CR-bit | Ffirst 3-bit mode (implicit zz=1)     |
 |RG|SNZ|VLI 1|inv|  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |

that preserves the 

and just have to specify that zz=1 implicitly for 3-bit mode.
if people *really* want dz=sz=0 (twin-predication or single)
then they can take a copy of the relevant CR-bit-vector
using "sv.mcrf/sm=X/dm=y" to perform the compress/expand...
and *then* do sv.cmpi/mrr

ohhh... sigh, really must do a unit test sv.mcrf/mrr/sm=x/dm=y

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