[Libre-soc-isa] [Bug 1087] add pseudocode to properly setup for fp traps according to PowerISA spec convention

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

--- Comment #37 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #36)

> > When `RT` is not written (`vex_flag = 1`), all CR0 bits
> > except SO are undefined.
> 
> https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;
> h=72076851a4927c15c077db046d2ec0a234033fa0

ok that's really clear. good catch that the wording also needed fixing.
interesting that it's not made clear in the Power ISA spec itself, i will
have to do a quick search for vex_flag

> commit 72076851a4927c15c077db046d2ec0a234033fa0
> Author: Jacob Lifshay <programmerjake at gmail.com>
> Date:   Thu May 25 22:09:31 2023 -0700
> 
>     fcvttg CR0 fields (except SO) are undefined when RT is not written

ok yes i forgot. been too long.  ok so implementation-wise vex_flag
needs to be done like overflow in ISACaller. see bug #1177.

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