[Libre-soc-isa] [Bug 1222] New: setvl Rc=1 needs to be more sophisticated

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1222

            Bug ID: 1222
           Summary: setvl Rc=1 needs to be more sophisticated
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

* when VL is set to greater than MAXVL (and truncated), CR0.GT is set to 1
* when VL is non-zero, CR0.LT is set to 1
* when VL is set to zero, CR0.EQ is set to 1

in that order because MAXVL might be zero.
overflow (CR0.SO) should be fine

this allows detection of some loop conditions that
are useful.  for example when detecting that VL is
set to a last value (between 0 and MAXVL) you know
that a loop is terminating, so sv.bc has no need
to branch back.  this *without* using CTR.

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