[Libre-soc-isa] [Bug 1055] update ls004 OPF RFC to include LD-ST-Shifted instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1055

--- Comment #24 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #22)
> (In reply to Luke Kenneth Casson Leighton from comment #21)
> > EA <- (RA) + (RB)<<(SH+1)
> 
> note the shift should be parenthesized like so:
> EA <- (RA) + ((RB) << (SH+1))
> so you don't accidentally have it trying to do:
> EA <- ((RA) + (RB)) << (SH+1)

I just checked, our parser currently has shifts as lower precedence than
addition, so it does parse RA + RB << shift as (RA + RB) << shift, which is
wrong here, so, shriya, luke, those shift expressions *need* to be
parenthesized.

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;h=d0a2630acad98e5092fffd5ab771ef7460f1fefa;hb=f3f8aff4aefa36e0af4c9afe2d6e5913d2e78328#l184

shifts being lower precedence than addition seems to match PowerISA v3.1B from
cursory examination:
see the pseudocode of vcmpequb, they have:
(all_true<<3) + (all_false<<1)

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