[Libre-soc-isa] [Bug 1055] update ls004 OPF RFC to include LD-ST-Shifted instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1055

--- Comment #17 from Jacob Lifshay <programmerjake at gmail.com> ---
I expect all instructions' pseudocode to be of the form:

shifted:
    EA <- (RA|0) + ((RB) << (SH + 1))
    load/store at address EA

postinc:
    EA <- (RA)
    load/store at address EA
    RA <- (RA) + (RB)

preinc-shifted:
    EA <- (RA) + ((RB) << (SH + 1))
    load/store at address EA
    RA <- EA

postinc-shifted:
    EA <- (RA)
    load/store at address EA
    RA <- (RA) + ((RB) << (SH + 1))

many of the recent pseudocode updates don't match that, e.g.:
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=fc695579c71a83592cfd2b91d41a60544dbd34a9

which is:
* ldupsx RT,RA,RB,SH

Pseudo-code:

    EA <- (RA)<<(SH+1)
    RT <- MEM(EA, 8)
    RA <- (RA) + (RB)

this doesn't look right to me, RB should be shifted, not RA, and the shift
should be on the increment, not EA

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