[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 31 09:13:32 BST 2023


--- Comment #3 from Paul Mackerras <paulus at ozlabs.org> ---
Has thought been given about what fishmv should do in exception conditions?
What if FRS contains a Signalling NaN initially? Should fishmv generate a
VXSNAN exception in that case? Or do you consider this to be a move-type
instruction (like fmr) which never generates exceptions?

Using SINGLE() and DOUBLE() in the RTL for fishmv means that overall the effect
is like doing stfs, sth (to the lower 16 bits), followed by lfs. One of the
things about stfs is that if the source FPR doesn't contain a valid
single-precision value (for example, a finite value that is too large to be
represented in single precision), the value stored to memory is essentially
garbage (the upper bits of the exponent and lower bits of the mantissa are

Are you OK with fishmv generating some result which is very different from the
input value in this kind of case? (If so, a programming note warning about the
possibility is probably appropriate.)

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