[Libre-soc-isa] [Bug 1062] OPF RFC ls005 iterative feedback and questions

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 31 08:04:59 BST 2023


--- Comment #7 from Paul Mackerras <paulus at ozlabs.org> ---
Thinking about this a bit further, the instruction description would not need
to mention the possibility of doing multiple elements in a register in the SV
case, because the SV iterations would take care of that. What would need to be
mentioned, though, is that the bits affected are not always the least
significant bits.

In other words, it isn't really sufficient for the RTL to say that bits
64-XLEN:63 of the relevant GPRs are used or modified. It needs to be something

64 - ((i + 1) * XLEN) : 63 - (i * XLEN)

where i is the element number within the GPR. In the non-SV case, i would
always be 0.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list