[Libre-soc-isa] [Bug 1080] allowing LD/ST-Update to select individual regsters needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1080

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #7)

> umm, you seem to have missed my point which is that programmers should write
> a scalar load instruction (sv.ldx r4, r5, r3) rather than sv.ld/sm=1<<r3 r4,
> 0(*r5) since simple cpus won't perform that optimization since that's more
> complex to do.

blech, costs an extra register (RB=r3) but it is the same thing... or is it?
ermermerm... oh! it isn't! not quite - it's a multiply/shift on r3.  and
needs a vector source.

no you can use /els then the immediate becomes a multiplier... let me
check, i can never remember

    if RA.isvec:
        svctx.ldstmode = indexed
    elif els == 0:
        svctx.ldstmode = unitstride
    elif immediate != 0:
        svctx.ldstmode = elementstride

and then:

        elif svctx.ldstmode == elementstride:
          # element stride mode
          srcbase = ireg[RA]
          offs = i * immed              # j*immed for a ST

and... oh hang on if you really want r3 as an index, you can do
element-strided on RB:

        if els and !RA.isvec and !RB.isvec:
            svctx.ldstmode = elementstride

        if svctx.ldstmode == elementstride:
            EA = ireg[RA] + ireg[RB]*j   # register-strided


so the syntax for that is:

   sv/ldx/els  *RT, RA, RB  # yes, just scalar on RB.

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