[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri May 26 22:48:29 BST 2023


--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
original comment https://bugs.libre-soc.org/show_bug.cgi?id=944#c5
please reply here

(In reply to Jacob Lifshay from

> i think it would be appropriate to rename the instructions like so:
> fmvis -> fmis (floating move immediate shifted, like addis)

that would come with a corresponding expectation of... oh wait
it does indeed shift the lower half up, doesn't it? that's a
hilarious quirk of BF16.

> fishmv -> either fmil (floating move immediate lower) or fmi2 (floating move
> immediate 2nd-half/part-2 -- allows future extension for fmi3/fmi4 for full
> bfp64 if desired)

hmm hmm i thought initially "yep you don't wanna do that because of
pfmis and pfmil", but i just realised that SVP64 would be punished
for it [no 96-bit instructions allowed].

so yes i like it.

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