[Libre-soc-isa] [Bug 1087] add pseudocode to properly setup for fp traps according to PowerISA spec convention

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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             Status|CONFIRMED                   |IN_PROGRESS

--- Comment #36 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #35)
> action required:
> 
> * NONE (no change) on the pseudocode
> * English language text stating "on exception CR0 fields UNDEFINED except
> CR0.SO"

I phrased it differently since that's not exactly correct (since I was glossing
over one case when discussing with you):

> When `RT` is not written (`vex_flag = 1`), all CR0 bits
> except SO are undefined.

https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=72076851a4927c15c077db046d2ec0a234033fa0

commit 72076851a4927c15c077db046d2ec0a234033fa0
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Thu May 25 22:09:31 2023 -0700

    fcvttg CR0 fields (except SO) are undefined when RT is not written

    this can occur even when fp traps are disabled in MSR, so writing
    "on exceptions" is incorrect.

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