[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1056

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Paul Mackerras from comment #8)
> "Definition of Strict Program Order" section:

> not require references to other architectures. Also, the Power ISA usually
> uses the term "Current Instruction Address" rather than "Program Counter",
> so the term "Sub Program Counter" should be replaced by "Current Iteration
> Counter" or similar.

i buy that. hmm are there any places where CI-SVSTATE needed to
know about NI-SVSTATE?


> I think what you are trying to say here is that (a) Simple-V defines a
> specific order to the iterations it performs,

yes.

> (b) the iterations must appear
> to the program to be executed in that order,

yes.

> and (c) the Current Iteration
> Counter is exposed in the SVSTATE SPR, allowing interrupts to be taken
> within the sequence of iterations. 

yes.  this is more obvious in Vertical-First Mode because SVSTATE.srcstep
and dststep etc. do not change (until executing svstep).


> (Point (c) may be Book III material in fact

i don't mind, if that's where it's best put.


> -- what happens if a program explicitly sets the Current Iteration
> Counter in SVSTATE to a non-zero value before executing an SVP64
> instruction?)

this is exactly what a Context-Switch Handler or a function call does!
therefore i had to both define it *and* then implement unit tests,
checking it.

answer: Sub-execution continues from whatever the CPU reads and interprets
from SVSTATE!

if SVSTATE.srcstep=1 then element 0 is *NOT EXECUTED*, because you
just very clearly requested execution to begin from element **1**.

it really is a loop, but implemented as a preemptive interruptible
Finite State Machine.  the ISACaller Simulator is hell to understand.
only 1000s of unit tests are holding it together.

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