[Libre-soc-isa] [Bug 1062] OPF RFC ls005 iterative feedback and questions

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu May 25 06:57:16 BST 2023


--- Comment #5 from Paul Mackerras <paulus at ozlabs.org> ---
Comments from IBM architects regarding LS005:

This is subject matter for which no degree of handwaving is acceptable. Every
last detail needs to be spelled out, perhaps not in final words, but in clear,
unambiguous descriptions. We would much prefer to scalarize or packed SIMD
vectorize into scalar registers using existing Vector/VSX instructions to avoid
the many pains associated with, for example, address generation using tiny

Is XLEN a fixed constant for a given implementation, or can it be programmed?

Other complications that need to be addressed include interaction with SPRs and
things like SPRs that have fixed lengths not subject to XLEN, how to do CMODX
(self-modifying code), assurances about atomicity of operations that need to be
atomic, etc.

Since the MMU depends on 64b addresses, it's hard to see anything smaller being
acceptable for privileged architecture. Might get away with 32b for problem
state. How does this apply to Vector and VSX? Although LibreSoC may not care,
the architecture needs to be complete.

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