[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1056

--- Comment #11 from paulus at ozlabs.org ---
Questions about vertical-first mode:

In a VF loop, how does each instruction indicate which operands should be
considered as vector operands? I think you would often want to have vector
operands in different places in different instructions in the loop.  For
example, one instruction might want to treat RA and RB as vector (but not RT)
and the next might want to treat RT and RA as vector (but not RB).

Is it the case that a 32-bit instruction with no SVP64 prefix within a VF loop
would have some Simple-V vectorization modifications applied to it? For
example, would an add instruction (just the 32-bit add instruction, no SVP64
prefix) be subject to the element size indicated in the SVP64 word (prefix) at
the start of the VF loop?

Or is it the case that if you want the vectorization modifications (e.g.,
element size specification) applied to an instruction, then you have to give it
a SVP64 prefix?

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