[Libre-soc-isa] [Bug 1087] change pseudocode to prevent output register write only when causing a fp trap and output is in same regfile as input

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

--- Comment #21 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #20)
> other *fun* side-effects of fcvtfg

whoops, I meant fcvttgo.

> not writing RT (if we decide to not
> accept my proposal) is that we either have to manually calculate CR0 in the
> pseudocode or not change CR0 (messes with data-dependent fail-first) or
> (probably the worst option) read RT and calculate CR0 from the read-in
> value. (CR1 doesn't have that problem since it's input always comes from
> FPSCR).
> 
> I think the best option is to just have fcvtfg

same here

> always write RT as I
> proposed, since suppressing writes (so the trap handler can see the input)
> is only necessary when targeting the same register file as inputs.

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