[Libre-soc-isa] [Bug 1080] allowing LD/ST-Update to select individual regsters needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 8 23:22:43 BST 2023


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)
> (In reply to Luke Kenneth Casson Leighton from comment #1)
> > (In reply to Luke Kenneth Casson Leighton from comment #0)
> > 
> > > lwzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
> > > stdux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
> > > 
> > > these become harder as the encoding space is only 6 bits (and there
> > > are 3 regs, RT/RS RA RB) due to Twin-Predication taking up 3 bits
> > > of EXTRA
> > 
> > this cannot be lost as it destroys VSPLAT VINDEX VGATHER VSCATTER
> please define VINDEX 

sm=1<<r3. or just sm=r3 where one bit is set. there is probably another
name for it.

>-- it is non-standard terminology -- do you mean
> load/store with index remap?

no. i would have said Indexed REMAP.

> predicate). The only load/store ops that need more than one predicate are
> compress/expand load/store

i.e. all of them (as far as the actual scalar ld/sts are concerned)

> iirc the plan was originally to have twin-predication only on 1-in/1-out
> operations, which ldux/stdux clearly are not.

the address (EA) is considered to be "1" in this case.

> > could ELWIDTH instead be considered, and the operation width
> > (ld lw lh lb) be used in its place?
> > 
> > * yes as long as losing saturation and sign-extending is ok.
> simple -- just set ELWIDTH larger than the load op and the load op
> intrinsically will do the sign/zero extend, no need for SVP64 to add
> sign/zero extension on top of that. (with the sole exception of signed
> bytes, thanks PowerISA for being non-orthogonal)

deep joy.

and it isn't _particularly_ useful to do shorter (load then truncate,
that's just dumb).

> saturation can still be done -- saturating from the load's type to the dest
> type (ELWIDTH + saturation's unsigned/signed bit).
> so this removes any need for ELWIDTH_SRC on any load/store ops afaict.

okaay. now we are cooking with gas.

next stage, given two free bits, is to work out what regs can be
expanded from EXTRA2 to EXTRA3.

* lwzux RT,RA,RB

if vectorised and used for list-pointer-chaining, it is RT and RA that
must be allowed to be one-different.  RB, because it is not updated,
need not be EXTRA3.

* stdux RS,RA,RB


aieee this is going to be fun.

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