[Libre-soc-isa] [Bug 1080] allowing LD/ST-Update to select individual regsters needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 8 20:01:35 BST 2023


--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #0)

> lwzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
> stdux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
> these become harder as the encoding space is only 6 bits (and there
> are 3 regs, RT/RS RA RB) due to Twin-Predication taking up 3 bits
> of EXTRA

this cannot be lost as it destroys VSPLAT VINDEX VGATHER VSCATTER

> MASK_SRC	16:18	Execution Mask for Source

so has to stay. that leaves just 6 bits to cover 3 registers.

here's the bits of RM:

Field Name      Field bits      Description
MASKMODE        0       Execution (predication) Mask Kind
MASK    1:3     Execution Mask
SUBVL   8:9     Sub-vector length
ELWIDTH 4:5     Element Width
ELWIDTH_SRC     6:7     Element Width for Source
EXTRA   10:18   Register Extra encoding
MODE    19:23   changes Vector behaviour

can't lose mask. can't lose SUBVL (priority for Pack/Unpack, already
discussed bug #1077). *could* consider ELWIDTH_SRC, what effect does
that have?

* Vector of RB offsets could no longer be compressed
* SEA becomes pointless

could ELWIDTH instead be considered, and the operation width
(ld lw lh lb) be used in its place?

* yes as long as losing saturation and sign-extending is ok.

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