[Libre-soc-isa] [Bug 1080] New: allowing LD/ST-Update to select individual regsters needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1080

            Bug ID: 1080
           Summary: allowing LD/ST-Update to select individual regsters
                    needed
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

offsets by one are only possible with EXTRA3 (or scalar registers).
some thought is needed on how to turn several LDST instructions
from EXTRA2 to EXTRA3.

see SV CSVs
https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isatables;hb=HEAD

stwu,LDST_IMM,,2P,EXTRA2,EN,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA

this is easy, make RA-src same as RA-dest

lwzu,LDST_IMM,,2P,EXTRA2,EN,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA

likewise.

lwzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
stdux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA

these become harder as the encoding space is only 6 bits (and there
are 3 regs, RT/RS RA RB) due to Twin-Predication taking up 3 bits
of EXTRA

Field Name      Field bits      Description
Rdest_EXTRA2    10:11   extends Rdest (R*_EXTRA2 Encoding)
Rsrc1_EXTRA2    12:13   extends Rsrc1 (R*_EXTRA2 Encoding)
Rsrc2_EXTRA2    14:15   extends Rsrc2 (R*_EXTRA2 Encoding)
MASK_SRC        16:18   Execution Mask for Source

Field Name      Field bits      Description
Rdest_EXTRA2    10:11   extends Rdest (R*_EXTRA2 Encoding)
Rsrc1_EXTRA2    12:13   extends Rsrc1 (R*_EXTRA2 Encoding)
Rdest2_EXTRA2   14:15   extends Rdest2 (R*_EXTRA2 Encoding)
MASK_SRC        16:18   Execution Mask for Source

some analysis of options and consequences is needed.

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