[Libre-soc-isa] [Bug 1077] evaluate removing /vec234 from instructions, move subvl to SVSTATE

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 3 05:20:39 BST 2023


--- Comment #8 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Dmitry Selyutin from comment #7)
> So we free 2 bits in RM (thus for each instruction) and move these two into
> SVSTATE (thus global).

or just remove subvl completely. this also conveniently frees up extra bits in
SVSTATE (no need for tracking subvector steps) so we can make VL larger for
future SVP64 versions and/or allows us to split MAXVL into OP_MAXVL and
REG_MAXVL as proposed in the prefix-sum bug's comments.

> Before doing this, few questions:
> 1. Do we have use for two bits freed in RM? Perhaps some specifiers can be
> simplified.

I think we should expand all register specifiers to 3 bits if possible, it'd be
nice to never have to worry about which registers can be encoded or not, since
that helps make register allocation that much more complex...

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