[Libre-soc-isa] [Bug 1077] evaluate removing /vec234 from instructions, move subvl to SVSTATE

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 3 04:12:52 BST 2023


--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> unfortuately, /vec2 doubles that.  /vec3 triples it. and unlike
> setting MAXVL, the  /vec are on a *per instruction* basis.  so
> one minute you reserve 5 regs, the next you reserve 10.

that applies equally to operations that write two registers such as dshl or all
the FFT ops.
> yes elwidth halves quarters etc. but that is less not more regs.
> if you look closely at ISACaller subvl is anomalous, and in
> Vertical-First Mode causes minor havoc.

that's cuz subvl basically says that the basic element type is a mathematical
2/3/4-vector rather than a scalar type...or at least that's what I intended.

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