[Libre-soc-isa] [Bug 1077] evaluate removing /vec234 from instructions, move subvl to SVSTATE

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 3 04:04:51 BST 2023


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
                 CC|                            |toshaan at vantosh.com

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this is a BIG spec change but it is one that is important to get right.

the issue is that SVSTATE is supposed to define in advance the
number of registers needed, so that hardware gets a head-start
on reserving space, does not reserve too much.

MAXVL is supposed to say "ok we have MAXVL=5, that means each
instruction could use only up to 5 regs, no need to speculatively
reserve 6" and you know that holds true until MAXVL changes.

unfortuately, /vec2 doubles that.  /vec3 triples it. and unlike
setting MAXVL, the  /vec are on a *per instruction* basis.  so
one minute you reserve 5 regs, the next you reserve 10.

yes elwidth halves quarters etc. but that is less not more regs.

if you look closely at ISACaller subvl is anomalous, and in
Vertical-First Mode causes minor havoc.

by moving subvl to SVSTATE we also free up 2 bits, there are no
RESERVED bits at all.

but SVSTATE only has 6 bits free. that would go down to 4.

thoughts appreciated

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