[Libre-soc-isa] [Bug 1046] questions and re-submission of ls001 (SVP64 concept)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1046

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
1. we *want* the Decoder to be identical (because anything else is just nuts in
hardware).
2. therefore i *thought* it was ok to request illegal instruction be raised on
non-vectorised areas whereas
3. doing so makes the Decoder more complex and
4. if the UnVectoriseable instruction is repeated actually it just... gets
repeated.

that said, it now occurs to me that there *is* actually an area (an
opportunity) for raising the Illegal Instruction not as part of the "Defined
Word" decoding, but as part of the "Mode Identification" Phase.

this phase is unavoidably necessary, and is required to provide the following
additional information:

* what is the instruction's category? Arithmetic, LDST, CRops or Branch?
  (this is exactly where "UnVectoriseable" may easily be added to the
  list)
* is it Twin or Single Predication
* How is the EXTRA2/3 area to be decoded? 1, 2, 3 or 4 regs?
* anything else (are 2 bits of EXTRA dedicated to SRC_ELWIDTH)

thi can be done *in parallel* with the Scalar "Defined Word" Decoding, and the
results of these two phases passed to the SVP64 Augpmentation phase: creation
of 7-bit GPR/FPR/CR-field numbers being the most important of these.

but this is a slight digression: the important fact answering your
question is that a category "No Category i.e. UnVectoriseable" can
easily be added and already has to be added because you need to stop
augmentation from happening.  particularly in OoO high performance
systems you can early-exit from the Decoding (because the first
phase was sufficient and the second stage of Augmentation can be
bypassed) which any OoO Hardware Engineer will appreciate the
opportunity to reduce pipeline stage length.

overall then i think although i was on the wrong initial track
(wrong decoder) the principle of raising Illegal Instruction on
UnVectoriseable is sound, causing no latency, because the information
to do so is available and available early.

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