[Libre-soc-isa] [Bug 1017] ISA WG RFC for binary and ternary bitops

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1017

--- Comment #19 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #18)
> a GPR-based version, especially when it wastes 60 bits out of 64,
> and especially as it will cause new datapaths to be created between
> the CR pipelines and the GPR Regfile, whose distance may be extremely
> long in IBM's layout, will go down badly.

Well, you're missing some critical differences between SVP64 and AVX512: CRs
already have to be close to GPRs because CRs are used basically everywhere in
instructions that use both GPRs and CRs:
isel -- x86's equivalents are very common.
cmp -- extremely common
setbc -- will be used basically everywhere (x86's equivalents are, compilers
have not caught up yet and still generate a 7-8 insn sequence of shifts, adde, 
and rotates for bool = i64 < i64)
every Rc=1 insn -- basically everywhere.

predicate registers are not close to GPRs in AVX512 because they're close *to
the simd registers*, in SVP64, those *are GPRs*. so, adding SVP64 makes having
CRs close to GPRs probably even more important than ever.
> 
> we are in other words taking a huge risk by loading CR Fields as
> Predicate Masks, but at the same time they are perfect for the
> job. it is a balance that requires some care and some modelling and
> guesswork of how IBM's extremely large IC might be designed, and
> to take that *existing* design into consideration.
> 
> those "extra" instructions provide a clean RISC-paradigm firebreak
> between pipeline units whose distance may be simply too far apart.
> forcing the CR and GPR regfile and pipelines to be close to each other
> may not go down well.

the way I see it, if they decide to substantially separate CR and GPR reg
files, that won't go down well, because of how often conditional branches are
used that source their data from cmp/Rc=1 ops:

according to https://oscarlab.github.io/papers/instrpop-systor19.pdf
on x86-64:
* test/cmp is 7.3% of all instructions
* je/jne is 7.5% of all instructions

so i likewise expect about 7% of *all* ppc64le instructions to be compares or
Rc=1 from GPRs into CRs so they can be used by a conditional branch.

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