[Libre-soc-isa] [Bug 1012] New: Iterative OPF ISA WG questions, feedback, and re-submission

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1012

            Bug ID: 1012
           Summary: Iterative OPF ISA WG questions, feedback, and
                    re-submission
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

Each Draft ISA RFC, once submitted, has to be reviewed for consideration
by the OpenPOWER ISA Working Group.  This process, for which RED
Semiconductor Ltd specifically joined the OPF ISA WG (and is under
Commercial Confidentiality), itself has multiple stages, including
review by several teams internally within IBM (the primary user of
the Power ISA). RED Semiconductor Ltd will take responsibility for
collating the questions and ensuring that permission
is granted by the ISA WG to publish the questions with neither an
NDA nor Commercial Confidentiality being violated, working as a
Member of the ISA WG to ensure that no Confidential Information provided
by OPF Members becomes public.  This is complex!

Also involved here may be documenting of modifications to SVP64 and/or
the Simulator(s) - the python-based ISACaller and the (new) cavatools
2021-08-071 Grant, bug #939.  The documentation of modifications is
part of this Milestone: the implementation of changes is not (that
should be covered by Grant 2022 08 107, bug #961.

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