[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Jun 22 12:02:20 BST 2023


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=1116

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
quick note: see bug #1116, the idea there is to make it possible
for ALL immediate instructions to load a Vector of immediates
(*from I-Cache* not D-Cache).

(In reply to Luke Kenneth Casson Leighton from comment #19)

> i would be fine with fli2 being a "shift and append", and even reducing
> down to just the one instruction fli where if FRA=0 it causes a
> reset (clearing) of FRT.
>     prevstuff <- (FRA|0)
>     FRT <- prevstuff << 16 || imm

i just realised it needs to be....

     prevstuff <- (FRA|0)
     FRT <- imm || prevstuff >> 16

because the immediates are BF16 encoding on first use.  is that right?
damn no it isn't.  it'll have to be:

     prevstuff <- (FRA|0)
     prevstuff <- SINGLE2DOUBLE(prevstuff)        # optionally
     result <- imm || prevstuff >> 16
     result <- SINGLE2DOUBLE(result)              # optionally
     FRT <- result

that may not be accurate, is it at least clear what i am trying to
communicate?  that:

* BF16 with one flis should get loaded in with just the one instruction
  and *still be useful*
* FP32 should be two flis instructions
* FP64 with the low mantissa bits all zero should be 3 flis ops
* full FP64 should be with four flis ops.

no additional instructions, no exceptions raised or required.

i have a sneaking suspicion that one extra bit is needed to get the
last two steps, i.e. to stop the DOUBLE2SINGLE and SINGLE2DOUBLE

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list