[Libre-soc-isa] [Bug 1015] rfc for rest of int/fp move/convert ls006

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1015

--- Comment #45 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #44)

> note mtfprd/mffprd 

which are not real instructions they are pseudo-aliases

> are just using the existing instructions

existing VSX instructions that will have their own Vectorisation Prefixing

>  but made
> available on SFFS when SX/TX=0, since PowerISA treats the SX/TX=0 version as
> a FP instruction instead of a VSX instruction. 

no. definitely not.  absolute total chaos would ensue: code would redirect
down an untested hardware path.

plus, the entire SV concept would become "non-orthogonal".
we have pushed hard for keeping entirely separate from VSX:
what you are effectively saying is to dig deep into VSX
Encoding and *redirect* to a different hardware path.
aside from losing the Orthogonality this will deeply complexify
Multi-Issue Decode.

> the only part that we would
> lose if we just used the existing instructions is Rc=1 support for fmvtg.,
> which is not that important.

which is a secondary reason to keep it

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