[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1092

Paul Mackerras <paulus at ozlabs.org> changed:

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--- Comment #20 from Paul Mackerras <paulus at ozlabs.org> ---
Here is a suggestion which you might like to consider, and which might be more
easily accepted by the IBM architects (no guarantees, I don't know what they
will think of it).

If you look at xxspltidp, it is actually quite close to what you want. It is a
prefixed instruction (using a PO1 prefix) which has 32 bits of immediate field
containing a single-precision value, which is converted to double precision and
stored into the two halves of a VSR.

My suggestion is to define a "floating load immediate single-precision" (flis)
instruction which differs from xxspltidp in only one bit in its instruction
encoding, specifically that bit 12 of the suffix would be 1 in flis vs. 0 in
xxspltidp. The difference in behaviour would be that flis would test MSR.FP
rather than MSR.VSX, it would only address the FPRs (so bit 15 of the suffix is
always 0), and it would only write one value (vs. two copies for xxspltidp).

This should add minimal extra work for implementations which have VSX already,
and it wouldn't use up any PO9 opcode space.

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