[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1092

--- Comment #15 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #14)
> (In reply to Luke Kenneth Casson Leighton from comment #13)
> > (In reply to Jacob Lifshay from comment #11)
> > > notes from meeting, in order to fit in po9 i think fmis/fmi2 should be
> > > replaced with 1 64-bit non-vectorizable instruction that loads a f32 to fpr
> > 
> > elwidth=FP16/FB16 has to be taken into consideration.
> 
> that can be done with:
> addi r3, 0, 0x1234
> sv.fmtg/w=f16 *f5, r3

alternatively fmi could be a 64-bit scalar instruction with a 32-bit immediate
and a 2-bit mode field:
fmi frt, mode, imm32

if mode = 0b00 then
    FRT <- DOUBLE(imm32) # load f32 as f64
else if mode = 0b01 then
    # load full f64
    FRT <- SINGLE((FRT)) || imm32
else if mode = 0b10 then
    # load f32/f16/bf16 in low half
    FRT <- [0] * 32 || imm32

load f32 as f64:
fmi f3, 0, 0x12345678  # loads DOUBLE(0x12345678)

load f64:
fmi f3, 0, 0x12345678
fmi f3, 1, 0x9abcdef0  # loads 0x123456789abcdef0

load f32/f16/bf16:
fmi f3, 2, 0x12345678  # loads 0x0000000012345678

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