[Libre-soc-isa] [Bug 924] potential major opcode allocation for SVP64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=924

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #18)
> note from meeting: bits 30-31 need to be available for 32-bit po9
> instructions for Rc

appreciated - unless there is a really *really* good reason i am
not going to worry about it.  first reason: breaking up the 24-bits
of SVRM starts to interfere with XO (in other encodings).
second, there is precedent for Rc being in bit 21

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/fields.text;h=6560b147

 773     Rc (21)
 774         RECORD bit.
 775         0    Do not alter the Condition Register.
 776         1    Set Condition Register Field 6 as described in
 777              Section 2.3.1,     'Condition  Register'     on
 778              page 30.

if the (extremely-limited) XO space of EXT900 is used up we don't get any more.

i'm trying to think of a way to drop svindex, setvl and svshape
(all Unvectorizable) in there whilst allowing svstep (which *is* Vectorizable)
to also not have to be a mandatory 64-bit length.

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