[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Jun 6 21:09:23 BST 2023


--- Comment #12 from Konstantinos Margaritis (markos) <konstantinos at vectorcamp.gr> ---
(In reply to Jacob Lifshay from comment #11)
> notes from meeting, in order to fit in po9 i think fmis/fmi2 should be
> replaced with 1 64-bit non-vectorizable instruction that loads a f32 to fpr
> po9 frt xo imm32
> frt <- DOUBLE(imm32)

I totally agree with this suggestion.
Currently in order to load a 64-bit constant, using fmis/fmi2, I have to load
4x16-bit immedates, do 2x shifts and 2x OR to produce the intermediate 32-bit
values, then do another shift and OR to produce the final constant. Such an
fmvi instruction will reduce this to just a single shift and OR.

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