[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Jun 2 15:06:17 BST 2023


--- Comment #50 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Paul Mackerras from comment #8)

> You say "and the four REMAP SPRs if in use at the time". How is an interrupt
> handler to know whether the REMAP SPRs are in use?

they are non-zero and the bits in SVSTATE are also non-zero.

    |32:33|34:35|36:37|38:39|40:41| 42:46 | 62     |
    | --  | --  | --  | --  | --  | ----- | ------ |
    |mi0  |mi1  |mi2  |mo0  |mo1  | SVme  | RMpst  |

having to perform a shift-and-mask on those bits, right in a
context-switch or function call pre- or post- amble, will
be *really* costly.

the solution to that is to add an SPR which has a "window"
onto those bits. will crossref here as it is the same
solution used by RISC-V debug/trap-emulate

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