[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Jun 1 01:14:28 BST 2023


--- Comment #43 from Paul Mackerras <paulus at ozlabs.org> ---
(In reply to Luke Kenneth Casson Leighton from comment #37)
> > (in LE, since that's always what svp64 uses for registers):
> it's way more than that: it's what the *Power ISA* uses for
> registers (all of them).  it took several hours review of the

This is a misunderstanding of endianness. Endianness concerns the relative
weighting of individually addressable pieces of a larger entity. GPRs and FPRs
don't have individually addressable pieces and hence don't have endianness.

You may perhaps be confusing the direction that carries propagate in arithmetic
with endianness. Carries always propagate from less significant to more
significant digits, because that's how arithmetic works. That is nothing to do
with endianness. The Power ISA for a very long time was exclusively big-endian,
but carries always propagated from less significant to more significant bits.

> spec on VSX (pretty much every instruction) to *deduce* that
> arithmetic is LE-ordered.  the key instruction which helped
> determine it was a VSX shift instruction, which had a worked
> example.

VSX does have individually addressable pieces of registers, in that the various
permute-class instructions can address individual bytes using an index. In
those cases the bytes are usually numbered left-to-right, so if anything, VSX
registers are big-endian. In v3.1 there have been some instructions added which
are "right-indexed", for example vpermr, which do things like "31-index" in the
RTL to get the effect of little-endian indexing of the bytes of the register.
So in that sense VSX registers can be considered to be of either endianness.

> (this is not actually spelled out clearly and explicitly in
> the Power v3.1 spec).

Saying "arithmetic is LE-ordered" is a meaningless statement, which would be
why it isn't in the ISA.

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