[Libre-soc-isa] [Bug 900] Continue work on Atomics extension

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=900

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
I just thought of a way to add atomic ops that don't need memory model work: we
simply define them in terms of the existing instruction sequences for the
atomic ops. this also means they are trivially interoperable with all existing
atomic ops.

e.g. relaxed fetch_add is currently:
https://rust.godbolt.org/z/eP974v3cf
# addr in r3, addend in r4, result in r5
.LBB0_1:
        lbarx 5, 0, 3
        add 6, 4, 5
        stbcx. 6, 0, 3
        bne     0, .LBB0_1

so amoadd r5, r4, r3 would be defined to be equivalent to the above code
(except not modifying CR0 or r6)

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