[Libre-soc-isa] [Bug 1071] add parallel prefix sum remap mode

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1071

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=1155

--- Comment #25 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from bug #1155 comment #43)
> not happening, i have said this before and it is inviolate and not
> to be discussed further under this bugreport as it is firmly out of
> scope. they can write directly to SVSHAPEs and take the consequences
> after reading the spec's warnings.

by choosing to not allow dynamic size on svshape instructions you are forcing
parallel reduction to be much less powerful than RVV (RVV supports dynamic
reduction sizes), since computing the right values of VL from the length is
complex enough that it really shouldn't be done by software (it would be maybe
10-20 instructions), hardware can be substantially more efficient since
computing the length is basically a sum of several simple-ish terms, where
carry-save adders shine.

Also, setvl reads from registers, if svshape reads from registers it behaves
very similarly in how the sv-prefix loop expander could have to wait for the
value to be computed, and you had no problems with setvl...

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