[Libre-soc-isa] [Bug 1071] maybe add parallel prefix sum remap mode

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1071

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)

> parallel reduction is a reduction aka has only one output, the rest of the
> output vector is intermediate results that aren't a prefix-sum. parallel
> reduction is basically 1/2 a prefix-sum operation.

ahh that second half of the tree in the image on the wikipedia page.
okaaay.

right.  yes, it's doable.  it's pretty seriously late in the day but
i like it.

ok.

so if SVyd is free... which it is...

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/simplev.mdwn;h=c350b3cf86fadcfdd22663c7119249e00328ff4a;hb=74a1b2ad43661599e3c3810f742149c17e83f542#l281

then at line 301 and 305 "if SVyd == 1 then set submode=0b10 0b11
instead of submode = 0b00 0b01 in SVSHAPE0 and SVSHAPE1 respectively.

then in svshape.py:
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/svshape.py;h=8b4533755a214d243b509ca20994a7b3ff651cdf;hb=74a1b2ad43661599e3c3810f742149c17e83f542#l166

line 170 needs sub-mode detection... or does it... no.
iterate_preduce_indices() is where sub-mode would be
looked at and the second half done.

do you want to have a go at that? keep it *real* simple - one step at a
time, can you add support for

* SVSHAPE.skip == 0b10 -> submode 10 (LH argument) parallel-prefix
* SVSHAPE.skip == 0b11 -> submode 11 (RH argument) parallel-prefix

line 30
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remap_preduce_yield.py;h=a8093803da46ef81a1254b2b2c5b00f153568578;hb=74a1b2ad43661599e3c3810f742149c17e83f542#l34

and you *should* just be able to add the 2nd half onto the end (line 43
onwards) and do

   "if SVSHAPE.skip in [0b00, 0b01]: return"

and that should basically be it.  add a *real* simple 2nd "demo()" function,
please *don't* go massively overboard, or make significant changes to this
code ok?

one step at a time, remap_preduce_yield.py first.

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