[Libre-soc-isa] [Bug 1057] split out all int/fp min/max ops into their own RFC ls013

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Apr 19 20:03:19 BST 2023


--- Comment #9 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #8)
> (In reply to Jacob Lifshay from comment #7)
> > while we're changing stuff, adding min[u]w/max[u]w would be useful, since
> > lots of programs often use 32-bit types, and PowerISA has *w variants where
> > they'd be different than the lower 32-bits of 64-bit variants.
> hmmm.... what other ISAs have them? i'm getting concerned about the number
> of *w variants.  are those present in VSX?

arm has smax on 32/64-bit scalar registers and presumably also umax/smin/umin.
arm also has atomic fetch-and-min/max
arm and Power also have unsigned/signed simd min/max. VSX has no scalar integer

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