[Libre-soc-isa] [Bug 1053] New: Separate Vector CRs containing CR8-CR127 from Scalar CR containing CR0-CR7

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1053

            Bug ID: 1053
           Summary: Separate Vector CRs containing CR8-CR127 from Scalar
                    CR containing CR0-CR7
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

we've been made aware that the use of CR Fields as both Vectors and
Predicate Masks could compromise multi-issue out-of-order systems
due to the massive Hazard Management it creates.

to ensure that *scalar* instructions are not "damaged" the idea is
to make instructions that mix and match from CR00-7 and CR8-127
raise Illegal Instruction traps, *with the exception* of 1-in 1-out
such as sv.mfcr and the sv.crweird group, which woud still be
restricted to singlr-scalar destination if the destination is CR0-CR7.

high-performance systems could therefore consider CR0-7 as
a *completely and literally separate* register file from
CR8-CR127.

the same concept could also hypothetically be applied to GPR and
FPR but the result coud damage Simple-V by restricting the number
of contiguous registers useable as Vectors: the existing scalar
GPR/FPR being 25% of SVP64's register range.

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