[Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=937

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #2)
> > it will need to be an overwrite (RT-as-source) in order to get it into
> > RM-1P-2S1D as dshrshd RT,RA,RB so that EXTRA3 may be used.  as 3-in 1-out
> > RT,RA,RB,RC there is no room for EXTRA3 it would be EXTRA2 which cannot
> > handle odd vector regnums except through svoffset
> 
> as mentioned on irc:
> https://libre-soc.org/irclog/%23libre-soc.2022-09-25.log.html#t2022-09-25T23:
> 24:46
> imho we should have a few variants if we need overwrite, since that makes it
> more flexible:
> > yes, it can be an overwrite variant, imho if we do that we should provide
> > several variants for each input we overwrite: e.g. RT = op(RT, RA, RB),
> > RT= op(RA, RT, RB), RT = op(RA, RB, RT), RT=op(0, RA, RB), RT=op(RA, 0, RB)

If we change the shifts to shift mod XLEN (specifically XLEN, not XLEN * 2)
instead of being signed shift, then we only need 8 ops total. This is like all
other PowerISA shifts. shifting by >= XLEN is unnecessary for the pcenc
algorithm in comment #2 and for bigint shift:
def shl_op(a, b, c):
    # just like x86 shld for 64-bit values
    v = (u64(a) << 64) | u64(b)
    v <<= c % 64
    return u64(v >> 64)

def shr_op(a, b, c):
    # just like x86 shrd for 64-bit values
    v = (u64(a) << 64) | u64(b)
    v >>= c % 64
    return u64(v)

* RT = shl_op(RT, RA, RB)
* RT = shl_op(RA, RT, RB)
* RT = shl_op(RA, RB, RT)
* RT = shl_op(0, RA, RB)
* RT = shr_op(RT, RA, RB)
* RT = shr_op(RA, RT, RB)
* RT = shr_op(RA, RB, RT)
* RT = shr_op(RA, 0, RB)

Unnecessary ops:
* RT = shl_op(RA, 0, RB) is just plain shl
* RT = shr_op(0, RA, RB) is just plain shr
* because the shift amount is never >= 64, sign/zero extension doesn't matter
since none of the output bits would differ, hence no signed-right-shift is
needed.

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