[Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Sep 25 22:14:17 BST 2022


--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

with the shift-up placing zeros into the LSBs if RC>0
can you explain clearly why the following alteration
is not correct for pcdec?

    elif RC < 0:
        v <<= -RC
        return u64(v>>64)  # return hi 64-bits
        v >>= RC
        return u64(v)  # return low 64-bits

this will be fun

    for i in range(len(out)):
        out[i] = dshrsd(inp[i + offset + 1], inp[i + offset], shift)

it will need to be an overwrite (RT-as-source) in order to get it into
RM-1P-2S1D as dshrshd RT,RA,RB so that EXTRA3 may be used.  as 3-in 1-out
RT,RA,RB,RC there is no room for EXTRA3 it would be EXTRA2 which cannot
handle odd vector regnums except through svoffset

the only thing is, reverse-gear needed on dshlsd to avoid overwrite.
which is fine.

RT,RA,RB would be X-Form which would reduce opcode pressure greatly.

prefix-sum btw is doable with mapreduce using the right offsets of
RT RA and RB (1 different) probably RT=RA+1

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