[Libre-soc-isa] [Bug 936] Decide if we want to change the spec so RC1=1 fail-first instructions always write all outputs up to and including failing element

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=936

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
yep agreed, RC=1 should write its results for DD FF mode.

btw if something more complex is needed (FFirst inv/crbit with
VLi i.e. not just eq/ne) then crand, cror can be used, even if
the cror is an apparent nop (sv.cror *0,*0,*0) it gives the chance
to walk (and test) the CRfield bits.

https://libre-soc.org/openpower/sv/cr_ops/

still have to properly code up crops, that they work at all in
sv/trans/svp64.py is a total coincidence of the similarity between
crops and normal mode.

-- 
You are receiving this mail because:
You are on the CC list for the bug.