[Libre-soc-isa] [Bug 936] New: Decide if we want to change the spec so RC1=1 fail-first instructions always write all outputs up to and including failing element

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=936

            Bug ID: 936
           Summary: Decide if we want to change the spec so RC1=1
                    fail-first instructions always write all outputs up to
                    and including failing element
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: normal
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: programmerjake at gmail.com
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

https://libre-soc.org/irclog/latest.log.html#t2022-09-24T01:48:29

programmerjake (talking about using fail-first for pcdec.):
> uuh, RC1=1 can't be used, since the spec says the results are never stored,
> only the CR outputs...the whole point of pcdec. is the RT output, without
> it it's mostly useless
> either that or the spec is unclear
> > Note that when RC1=1 the result elements are never stored, only the CR Fields.
> https://libre-soc.org/openpower/sv/normal/#index5h1
> imho the spec should be changed to always write outputs for each element up
> to and including the first one that fails the data-dependent fail-first
> test, only elements after that one are not executed. VL being set to exclude
> the failing element should happen after.
> that way, an element is always fully-executed or not executed. not
> partially-only-writes-CR-executed
> all outputs, RT, CR, OV, etc.

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