[Libre-soc-isa] [Bug 933] prefix-code (like huffman code) decode/encode instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=933

--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #25)
> 56,ALU,OP_PCDEC,0,....1,0,NONE,0,0,pcdec,
> 57,ALU,OP_PCDEC,0,....1,0,NONE,0,0,pcdec,
> 
> those columns, NONE corresponding to "rc", should i think be "1"
> 
> i'll try it out.

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=38802b1df42b147ebaa413e65c872510279b1429

yep all good.

 56,ALU,OP_PCDEC,0,....1,0,ONE,0,0,pcdec,
 57,ALU,OP_PCDEC,0,....1,0,ONE,0,0,pcdec,

that's the "trick" for not needing Rc=1.  we're good to go with
CR0 as CRout, then.  meaning that sv_analysis.py can remain as this:

     elif regs == ['RA', 'RB', 'RC', 'RT', '', 'CR0']:  # pcdec

what a hatchet-job.  it works though.

the results aren't what is expected, i'll leave that to you to
sort out, but RS is written to, CR0 is written to, it's all there.

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