[Libre-soc-isa] [Bug 928] New: ld/st with shift

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Sep 21 00:26:12 BST 2022


            Bug ID: 928
           Summary: ld/st with shift
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: programmerjake at gmail.com
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

couldn't find a bug for this, so making one.

ld/st with shift isn't very useful for rt = mem((ra << sh) + imm) unless imm is
>25-bits or so, so instead i think the ops we'll want are (only listing loads
here, stores are analogous):
rt = mem(pc + (rb << sh) + imm) -- can be encoded by ra=0

rt = mem(ra + (rb << sh) + imm)

we'll also want a way to enable bounds checking and base addr. addition for
webassembly, so imho we reserve the max sh value (for 3-bit, that'd be sh=7) to
enable wasm addressing mode instead of shifting. for details, see

we could alternatively reserve sh=0 for wasm, since that's redundant with the
existing ld/st ops and that allows sh to reasonably be only 2 bits if we're low
on space. imho reserving sh=0 seems like the best idea in retrospect.

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