[Libre-soc-isa] [Bug 926] New: add with carry from CR field

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Sep 12 03:08:02 BST 2022


            Bug ID: 926
           Summary: add with carry from CR field
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

a vector add-with-carry is traditionally in-element, not
(as is the case with sv.adde) an alias for biginteger add.

weirdly all the adds in Power ISA do not have a variant
that takes CR Fields as carry-in producing carry-out.
slightly awkward is the fact that this may need to have
an Rc=1 variant as well, producing *two* CR Fields.

a workaround on that would be to leverage the CR.SO field
as both the carry-in and carry-out.

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