[Libre-soc-isa] [Bug 905] create Scalar reg access encoding (SVP64-Single)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Sep 11 14:41:54 BST 2022


--- Comment #11 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
> (In reply to Jacob Lifshay from comment #8)
> > i meant to saturate float to the range of those int types, not to convert to
> > an int and back. e.g. 23.5 saturating to u8's range is 23.5, but 300.25 goes
> > to 255.0.
> *click*. using dest elwidth.

*not* using dest elwid (unless it's repurposed for this and not elwid when
saturation is enabled). if you have a f32 you may want to saturate to u16 range
with a f32 result...

>  i like it.
> is starting to encroach on the reserved space though.
> if nothing else they can be added on top of those
> MODULO-FP operations.
> (In reply to Jacob Lifshay from comment #9)
> > if you're working on the ldst-with-shift, 
> heck no.  way too much else to do.
> > 7 -- wasm mode -- rb indexes bytes -- exact process determined by SPRs (TBD)
> SPRs controlling something as lowlevel and critical as LDST now requiring
> *five* 64-bit read ports and two writes? not a snowball in hell's chance
> that would get through the ISA WG, the IBM POWER Architects would take
> an extremely dim view of such costly operstions.

it's fine if they're somewhat more expensive, wasm ld/st isn't a standard ld/st
op. they are necessary for wasm performance though, unless you like a 30%
performance hit due to constantly needing several more instructions for each

> ldst-with-shift is already pushing the limits.
> you really do need to think through the regfile port allocation and
> Hazard Management implications, jacob,
> you can't just blithely throw features in without thinking through
> the micro-architectural implications.

those sprs can be assumed to rarely change, allowing them to be cached at the
ld/st alus and requiring a full pipeline flush each time they're changed --
that way they don't need dependency tracking or extra register read ports or a
pile of extra wires into the ld/st alus.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list