[Libre-soc-isa] [Bug 905] create Scalar reg access encoding (SVP64-Single)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Sep 11 14:30:26 BST 2022


--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #8)

> i meant to saturate float to the range of those int types, not to convert to
> an int and back. e.g. 23.5 saturating to u8's range is 23.5, but 300.25 goes
> to 255.0.

*click*. using dest elwidth.  i like it.
is starting to encroach on the reserved space though.

if nothing else they can be added on top of those
MODULO-FP operations.

(In reply to Jacob Lifshay from comment #9)
> if you're working on the ldst-with-shift, 

heck no.  way too much else to do.

> 7 -- wasm mode -- rb indexes bytes -- exact process determined by SPRs (TBD)

SPRs controlling something as lowlevel and critical as LDST now requiring
*five* 64-bit read ports and two writes? not a snowball in hell's chance
that would get through the ISA WG, the IBM POWER Architects would take
an extremely dim view of such costly operstions.

ldst-with-shift is already pushing the limits.

you really do need to think through the regfile port allocation and
Hazard Management implications, jacob,
you can't just blithely throw features in without thinking through
the micro-architectural implications.

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