[Libre-soc-isa] [Bug 905] create Scalar reg access encoding (SVP64-Single)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Sep 11 11:24:16 BST 2022


--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)
> (In reply to Jacob Lifshay from comment #2)
> > > 
> > > totals 21, 3 spare. EXTRA5? leave as reserved?
> > 
> > imho we should leave as reserved because that reduces the amount of space
> > required to 1/4th (accounting for 2 saturate bits) as much as svp64, greatly
> > reducing opcode pressure.
> though maybe use 1 bit so loads/stores can be pc-relative, like the v3.1
> prefix's R bit. this can greatly reduce needed instruction counts to access
> constants/variables, though imho we should differ from v3.1's R bit:
> we should always add (RA|0) and just tack on CIA as a new addend, rather
> than replacing (RA|0) with CIA, this allows stuff like keeping jump tables
> and other lookup tables easily accessible:

iiinteresting. like it.

especially on ldst-with-update, that would give an address in RA that
could then be used with normal-ldst

but... ah hang on, remember the nightmare lesson learned from trying
to do ld-st-with-shift?  this pc-relative bit is along those lines:
it's modifying instruction behaviour, and prohibiting vectorised-variants
from being able to do them.

it would actually be better i feel to propose these ldst-with-pc-relative
as new instructions (within the next EXT2nn group) and let them be
Vectorised (orthogonally).

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