[Libre-soc-isa] [Bug 905] create Scalar reg access encoding (SVP64-Single)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=905

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> thinking out loud for bitallocations
> 
> * 12 EXTRA4x3

alternately 12 EXTRA3 x4

> * 4 src/dst 2x2 elwidth
> * 4 predicate mask 1 type 3 select
> * 1 saturate

2 saturate -- unsigned/signed saturate differently, we'll want both -- this
should be encoded as a signed/unsigned bit and a saturate bit, since the
signed/unsigned bit is also useful for deciding to sign/zero extend
inputs/outputs when src/destelwid differ.

also fp ops have different values worth saturating to:
* standard 0.0 to 1.0
* standard -1.0 to 1.0
* i32? u32? i8? u8? i16? u16?

> 
> totals 21, 3 spare. EXTRA5? leave as reserved?

imho we should leave as reserved because that reduces the amount of space
required to 1/4th (accounting for 2 saturate bits) as much as svp64, greatly
reducing opcode pressure.

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