[Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=960

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #16)

> ok. do note that adde/subfe has the exact same issue,

i am planning a CR-field-base add for exactly that reason.

> for muledsbs (signed bigint * signed word), we may be stuck with the
> non-independently-parallelizability (sorta, OoO can run multiple vectors in
> parallel if the queues are big enough) because it's looking like 64 bits
> isn't enough carry bits, we may need it to also read/write CA:

absolutely not.  that is 4-in 3-out including XER.  please stop spending
time on that instruction, i will never put it forward to the OPF ISA WG.

for future reference, the hard limit is 3-in 2-out.  i will never put
forward to the ISA WG anything over that.  (the GF polynomial ops are a
special case as the entire ALU has a global polynomial which, if changed,
causes a multi-cycle stall)

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