[Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=960

--- Comment #16 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #15)
> (In reply to Jacob Lifshay from comment #14)
> 
> > why not? 
> 
> parallel processing of independent inputs and production of independent
> parallel results.
> 
> one single SPR prohibits such programming constructs.

my point was that, for that particular subset of instructions (mostly just
signed bigint * [un]signed scalar), support for such programming constructs
aren't needed, because software will always want to either use it in
dependency-chain mode (where speedups come from wide mul e.g. 256x64->320-bit
mul) or can easily use instructions not in that subset to achieve the desired
result, hence the restriction isn't preventing any usecases.
> 
> the loss of this option is not acceptable.

ok. do note that adde/subfe has the exact same issue, and you're apparently
fine with there not being a vector of CA flags...

we can just remove Rc from dsld/dsrd if needed to make space. imho signed
bigint ops are waay more necessary than Rc on dsld/dsrd since they save a bunch
of instructions.

for muledsbs (signed bigint * signed word), we may be stuck with the
non-independently-parallelizability (sorta, OoO can run multiple vectors in
parallel if the queues are big enough) because it's looking like 64 bits isn't
enough carry bits, we may need it to also read/write CA:
working pseudocode so far:

def muledsbs(ra, rb, rc, ca):
    if not ca:
        v = rc
    else:
        v = zext(rb + rc, xlen)
    v = sext(ra, xlen) * sext(rb, xlen) + sext(v, xlen)
    rt = zext(v, xlen)
    rs = zext(v >> xlen, xlen)
    ca = sext(ra, xlen) < 0
    return rt, rs, ca

-- 
You are receiving this mail because:
You are on the CC list for the bug.