[Libre-soc-isa] [Bug 960] OPF ISA External RFC ls003 - maddedu and divmod2du

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=960

--- Comment #14 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)
> (In reply to Jacob Lifshay from comment #12)
> > (In reply to Luke Kenneth Casson Leighton from comment #11)
> > > and i just realised, for parallel mode (RS=RT+MAXVL)
> > > a whopping 127 SPRs are needed. drat.
> > 
> > the instructions just won't support RS=RT+MAXVL
> 
> that's not acceptable.

why not? if they have a spr output instead, then they don't even have RS or RC
at all. why force them to implement a mode that isn't very useful for software
(it isn't useful because we specifically limited the spr-versions to those ops
where users always want that would be the RS=RC mode) when the motivating
reason for having that RS=RT+MAXVL mode ceases to be valid?

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